The fabrication of high aspect ratio features in silicon is used extensively in the manufacture of micro-electro-mechanical-systems (MEMS) devices. Such features frequently extend completely through the silicon wafer and may require etching in excess of 500 μm into the silicon substrate. Even “shallow” features require etch depths up to 30 μm with feature widths as small as 1 μm, requiring the definition of structures with aspect ratios (depth/width) in excess of 30:1. To ensure economically feasible manufacturability, these processes must operate at high etch rates to maintain reasonable throughputs.
Conventional, single step, plasma etch processes cannot simultaneously meet these needs, and, thus alternative deposition/etching processes have been developed. For example, the process disclosed in U.S. Pat. Nos. 4,985,114 and 5,501,893 use a high density plasma source, typically an Inductively Coupled Plasma (ICP), in conjunction with a radio frequency (RF) biased substrate electrode. Sulfur Hexafluoride (SF6) is used as the etch gas and gases such as CCl4 (U.S. Pat. No. 4,985,114) or C4F8 (U.S. Pat. No. 5,501,893) as the deposition gas. The process alternates with an interval of a few seconds between these two gases and results in silicon etch rates greater than 5 μm/min with high aspect ratios and deep etches into silicon substrates. It should be noted that other high density plasma sources such as Electron Cyclotron Resonance (ECR) or Helicon can be used.
Certain MEMS devices require that the silicon substrate be etched down to a buried insulating layer, such as a silicon dioxide (SiO2) layer, which acts as an etch stop. This structure is known as a Silicon On Insulator (SOI) structure which is required for functionality of the final device. When such structures are etched using a method such as disclosed in the '114 or '893 patent, “notching” occurs, which is a common reference to a well-documented phenomenon. Notching is evidenced as a severe undercutting of the silicon, localized at the silicon/insulator interface. It is generally understood that notching is caused by electrical charging effects during etching. Such effects are not present during the bulk etch because the silicon substrate is sufficiently conductive to ensure that current flow within the substrate prevents any charge separation. When the etch reaches the interface, the insulator is exposed and the conductive current path is broken, which allows charge separation to occur. Because of the different angular distributions of ions and electrons in the plasma, ions (+ve charge) tend to accumulate at the bottom of the feature, and electrons (−ve charge) at the top. The resultant electric field is strong enough to bend the trajectories of arriving ions into the feature sidewall where lateral etching (notching) occurs. See K P Giapis, Fundamentals of Plasma Process-Induced Charging and Damage in Handbook of Advanced Plasma Processing Techniques, R J Shul and S J Pearton, Eds, Springer 2000.
The notching effect is more prevalent in high density plasmas, because the ion density, and therefore the charging effect due to the ions, is greater. The effect can be reduced by the use of a low density plasma, such as in conventional reactive ion etching (RIE), which is employed only after the insulator has been exposed. See Donohue et. al. U.S. Pat. No. 6,071,822. The major drawback of such an approach is the low etch rate attainable, which is a serious shortcoming when features with various depths must be etched. This is a necessary consequence of etching devices with various feature sizes, which will etch to different depths due to Aspect Ratio Dependent Etching (ARDE).
The use of low frequency substrate bias in conjunction with an alternating deposition/etch process has been described as a solution to the notching phenomena, see Hopkins et. al. U.S. Pat. No. 6,187,685. The same inventors also describe the use of a pulsed RF bias in conjunction with a high density etch process as an alternative means of reducing notching. Hopkins describes pulsing of the high density source (ICP) but concludes that this is ineffective in eliminating notching, and therefore teaches away from this approach as a possible solution.
U.S. Pat. Nos. 5,983,828, 6,253,704 and 6,395,641 by Savas teach the use of a pulsed ICP to alleviate surface charging and subsequent notching. More specifically, in the U.S. Pat. No. 5,983,828, Savas teaches pulsed ICP for eliminating notching, but limits the ICP operating powers to greater than 5 kW. In the U.S. Pat. Nos. 6,253,704 and 6,395,641, Savas teaches pulsed ICP in conjunction with pulsed RF biased power. However, none of the pulsed ICP disclosures by Savas describe or suggest the use of pulsed ICP to eliminate notching for multi-step processes consisting of alternating deposition and etching steps.